Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology - Electronics Letters
نویسندگان
چکیده
Introduction: The increase of transistor speed in CMOS technologies has been reached mainly by scaling the gate length of the MOS transistors. For the most advanced technologies, gate lengths down to 40 nm with an ft of 243 GHz [1] have been reported. This allows performances comparable to expensive III-V technologies based on GaAs or InP and in addition the potential for very large scale integration (VLSI) designs. The speed performance of a technology for digital applications is characterised by minimal gate delay at a specified fan-out. Ring oscillators or delay chains are frequently used for the determination of the minimal gate delay of a technology.
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